GitHub

HTL8254 82C54 Compatible Programmable Interval Timer IP core

The HTL8254 IP core is written in vendor neutral VHDL and as such can be simulated by any simulation tool. The testbench however uses Siemens’ Modelsim SignalSpy in order to provide a non-intrusive ...
IEEE

Integrating Verilog Simulation with Python Automation: A ModelSim and Colab Framework for FPGA Design and Analysis

Abstract: Field-Programmable Gate Arrays (FPGAs) are pivotal in modern hardware development, offering a flexible and efficient platform for implementing digital systems. Traditional workflows for FPGA ...
IEEE

Efficient and Accurate Simulations of Metamaterials Based on Domain Decomposition and Unit Feature Database

Abstract: Recently, there has been tremendous interest in studying electromagnetic (EM) metamaterials. However, the full-wave simulations of large and complex metamaterials are challenging. This work ...