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Sweeney won the Top Presentation Award for his talk titled, “The SUMO Balancing Act: Insights into Cellular Robustness from ...

Abstract: A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in ...

Abstract: This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while ...