IEEE

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Abstract: In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure ...
IEEE

Enhanced Performance SRAM Design using 7nm FinFET Technology: Optimization of Propagation Delay and Power Consumption

Abstract: This research implements a 7nm FinFET-based 7T SRAM cell, designed using Xschem and simulated with Ngspice. The primary emphasis of this research aimed at reducing the propagation delay and ...