EDN

Compiler and instruction-set simulator suit designs with configurable processors

Tensilica’s V6 suite of automation tools has a pipeline-accurate instruction set simulator , the Xtensa C/C++ compiler, and the Xpres compiler. The suite understands variable-length flexible-length ...
Design-Reuse

Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Design-Reuse

New Synopsys ASIP Designer Tool Speeds Development of Application-Specific Instruction-Set Processors by 5X

Synopsys, Inc. (Nasdaq:SNPS) today announced availability of its new ASIP Designer tool that speeds the design of application-specific instruction-set processors (ASIPs) and programmable accelerators.
EDN

Processor Designer Tool Enables KYOCERA Design Team to Reduce Overall Project Schedule by Nine Months

Synopsys' ASIP design tools enable rapid exploration and optimization of processor architectures KYOCERA created a custom high-performance DSP in less than a year, saving an estimated nine months on ...